Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/Allwinner/D1H/TWI[2]/TWI_CCR#0x0
clk_duty=P50
TWI Clock Control Register
Setting duty cycle of clock as master
0 (P50): 50%
1 (P40): 40%
https://github.com/cmsis-svd/cmsis-svd-data